1. Field of the Invention
The present invention relates to a cold cathode fluorescent lamp (CCFL) and in particular to a method of optimally operating the CCFL. This method includes adjusting the frequency of the driving waveform followed by adjusting the duty cycle of the driving waveform.
2. Description of the Related Art
Liquid crystal displays (LCDs) are well known in the art of electronics. One of the largest power consuming devices in a notebook computer is the backlight for its LCD. The LCD typically uses a cold cathode fluorescent lamp (CCFL) for backlighting. However, the CCFL requires a high voltage AC supply for proper operation. Specifically, the CCFL generally requires 600 Vrms at approximately 50 kHz. Moreover, the start-up voltage of the CCFL can be twice as high as its normal operating voltage. Thus, over 1000 Vrms is needed to even initiate CCFL operation.
In optimal applications, the battery in the notebook computer must generate the high AC voltages required by the CCFL. To increase valuable battery life, an efficient means is needed to convert this low voltage DC source into the necessary AC voltage. In the prior art, magnetic transformers, have provided the above-described conversion. However, in light of ever decreasing space limitations, magnetic transformers are becoming impractical in notebook applications.
To this end, piezoelectric transformers, which are generally much smaller than their magnetic transformer counterparts, are increasingly being used to provide the DC/AC conversion for the CCFL. A piezoelectric transformer (PZT) relies on two inherent effects to provide the high voltage gain necessary in a notebook application. First, in an indirect effect, applying an input voltage to the PZT results in a dimensional change, thereby making the PZT vibrate at acoustic frequencies. Second, in a direct effect, causing the PZT to vibrate results in the generation of an output voltage. The voltage gain of the PZT is determined by its physical construction, which is known to those skilled in the art and therefore not described in detail herein. Because the PZT has a strong voltage gain versus frequency relationship, the PZT should be driven at a frequency relatively close to its resonant frequency (e.g. within 10%).
FIG. 1A illustrates a prior art CCFL circuit 100A described in U.S. Pat. No. 6,239,558, issued to Fujimura et al. on May 29, 2001 (hereinafter Fujimura). CCFL circuit 100A includes two input lines 102 and 103 for controlling a half-bridge formed by p-type transistor 104 and n-type transistor 105. Input lines 102 and 103 receive non-overlapping clock signals, as shown in FIG. 1B. In one embodiment, clock signal 121, which is provided to the gate of p-type transistor 104, can vary between the voltage VBATT provided by a battery 101 (thereby turning off that transistor) and VBATT−VGS, wherein VGS is the gate to source voltage of transistor 104 (thereby turning on that transistor). In this embodiment, clock signal 122, which is provided to the gate of n-type transistor 105, can vary between voltages VGS (thereby turning on that transistor) and VSS (e.g. ground)(thereby turning off that transistor).
Optimally, either p-type transistor 104 or n-type transistor 105 is conducting at any point in time, thereby providing a pulsed square waveform at node N1 that varies between VSS and VBATT. However, realistically, some delay between conducting states of transistors 104 and 105 must be present for reliable operation. Thus, for example, delays 119 and 120 associated with clock signals 121 and 122 can be included to ensure that transistors 104 and 105 are not conducting at the same time, thereby preventing an undesirable energy loss.
In CCFL circuit 100A, an inductor 106 and a capacitor 107 function as a filter to transform the pulsed square waveform at node N1 into a sinusoidal waveform at node N2. Note that a PZT 108 of CCFL circuit 100 typically includes a large input capacitance. Therefore, in some embodiments, capacitor 107 can be eliminated.
PZT 108 includes two input terminals (represented by two horizontal plates in FIG. 1A) coupled respectively to node N2 and VSS as well as one output terminal coupled to a node N3. Of importance, the sinusoidal waveform at node N3 (at the output of PZT 108) has greater amplitude than the sinusoidal waveform at node N2 (at the input of PZT 108). In this manner, the input terminal of CCFL 110 receives a high potential AC signal.
The output terminal of CCFL 110, i.e. node N4, is coupled to VSS via a resistor 113. As explained by Fujimura, the current flowing through resistor 113 can be sensed at node N4 via line 118 and then converted from AC to DC using a rectifier (typically including one or more diodes to force the current in one direction) to provide a voltage that is proportional to the CCFL current. An error amplifier EA compares this rectified voltage to a set reference voltage and then outputs the difference between the two voltages as an amplified comparison result. This amplified signal controls a voltage-controlled oscillator (VCO) that outputs a frequency signal to a drive circuit. This drive circuit provides the non-overlapping clock signals to transistors 104 and 105.
Thus, the above described control loop uses frequency to control the current through CCFL 110. Specifically, as known by those skilled in the art, PZT 108 has a characteristic frequency response. FIG. 1C illustrates a graph plotting the voltage gain versus frequency for PZT 108, assuming that the effects of inductor 106 and capacitor 107 are ignored. Typically, as indicated by an output voltage curve 150, an initial driving frequency 151 of the PZT is started high and then reduced until the voltage gain exceeds a reference voltage 191, which corresponds to a CCFL minimum starting voltage (for example, to voltage gain 152). At this point, the CCFL begins operation, thereby introducing a load to the PZT, as indicated by output voltage curve 160.
The PZT attains optimal performance at its resonance frequency, i.e. at resonance frequency 163. However, the frequencies starting close to zero and increasing to resonance frequency 163 result in unstable and/or inefficient operation of the PZT and thus are not used. Therefore, during CCFL operation, the PZT is preferably maintained between frequencies 161 and 162.
Of importance, and referring back to FIG. 1A, varying the driving frequency of the non-overlapping clock signals on lines 102 and 103 has corresponding frequency changes on the pulsed waveform at node N1 and the sinusoidal waveform at nodes N2 and N3. As the frequency of these waveforms changes, the current through CCFL 110 also changes.
One of the disadvantages of CCFL circuit 10A is that a large change in input voltage-provided by battery 101 (e.g. 7-24 V) causes the driving frequency to vary widely. In particular, at high input voltages the driving frequency may increase significantly to maintain the tube current at the desired value. However, as noted with respect to FIG. 1C, the most efficient PZT operation occurs near resonance frequency 163. Therefore, a high frequency can force PZT 108 into an inefficient area of operation (i.e. into a low gain area).
FIG. 1D illustrates a CCFL circuit 100B, also described by Fujimura, for regulating the output voltage of PZT 108 by controlling the duty cycle. Note that similar reference numerals in the figures refer to similar components. In CCFL circuit 100B, resistors 111 and 112 are connected in series between node N3 and VSS, thereby forming a voltage divider. In this manner, a line 117 connected to node N5 between resistors 111 and 112 can be used to detect the output voltage of PZT 108 at node N3.
Once again, an error amplifier EA compares the rectified voltage to a set reference voltage. The amplified EA output signal controls a pulse width modulation (PWM) oscillation circuit. The output of the PWM oscillation circuit, in turn, controls the duty cycle of a driving waveform to the driver, which generates the non-overlapping clock signals to transistors 104 and 105. In one embodiment, as the duty cycle of this driving waveform increases, p-type transistor 104 conducts longer and n-type transistor 105 conducts less, thereby increasing the amplitude of the signal at node N3.
Thus, the control loop of CCFL circuit 100B attempts to regulate the brightness of CCFL 110 by controlling the duty cycle of the driving waveform to the driver based on the amplitude of the sinusoidal waveform at node N3. In an alternative embodiment described by Fujimura, resistors 111 and 112 can be connected to node N2 via line 116. This control loop would attempt to regulate the brightness of CCFL 110 by controlling the duty cycle of the driving waveform to the driver based on the amplitude of the sinusoidal waveform at node N2. However, because the sinusoidal waveform at nodes N2 and N3 are not symmetric about ground, a standard rectification scheme could incorrectly identify the midpoint of the sinusoidal waveform. Thus, the above-described control loops can incorrectly adjust the brightness of the current through CCFL 110. Therefore, a need arises for an improved system for powering a CCFL.